1. Field of the Invention
The present invention relates to semiconductor devices and components. Particularly, the present invention relates to at least partially packaging a semiconductor die or dice. The present invention also relates to forming conductive elements such as traces, vias, and bond pads. In addition, the present invention relates to a microlens for directing light toward a photosensor, methods of forming same, and systems so equipped.
2. Background of Related Art
The invention pertains to a method for sealing and protecting at least the periphery of one or more semiconductor dice. When a semiconductor die is conductively attached to a carrier substrate, conventionally encapsulating the assembly is very desirable to enhance the mechanical bond between the die and the substrate and to mutually laterally electrically isolate adjacent electrical connections therebetween. More specifically, one common configuration for electrically connecting a semiconductor die is a so-called flip-chip package, wherein an array or pattern of external conductive elements, such as solder bumps or conductive or conductor-filled epoxy pillars, protrude from the active surface of the semiconductor die for use in mechanically and electrically connecting the semiconductor die to like-patterned ends of conductive traces of higher level packaging, such as a carrier substrate. Other semiconductor die configurations may include a die mounted to a lead frame (having a die mounting paddle configuration, or in a paddle-less leads-over-chip (LOC) configuration, or in a leads-under-chip (LUC) configuration) and, optionally, mounted to a carrier substrate in a chip-on-board (COB) or board-on-chip (BOC) arrangement, or in other packaging designs, as desired.
Conventional encapsulation typically involves transfer molding an encapsulant, usually a particulate silica filled thermoset, to substantially surround a semiconductor die electrically connected and mechanically affixed to a carrier substrate. Transfer molds typically comprise a bottom mold and an upper mold, wherein the mold halves may be mated to one another to form a plurality of predefined cavities, wherein usually one predefined cavity receives one of a plurality of semiconductor dice. Each semiconductor die may be placed within the cavity and encapsulant may be forced into each of the plurality of cavities to form an encapsulation structure that encapsulates the semiconductor chip and portions of the lead frame or carrier substrate.
In operation, a heated, silica-filled resin mold compound, usually a thermoset, is heated to a molten state, forced under pressure through runners into and through the mold cavities, wherein semiconductor die assemblies comprising semiconductor dice with attached lead frames or substrates are disposed (usually in strips or other groups, so that a group of six semiconductor dice, for example, would be placed in and across six cavities formed by the molds). After molding, the encapsulated semiconductor die assemblies may be ejected from the cavities by ejector pins, after which they may be post-cured at an elevated temperature to complete cross-linking of the resin mold compound, followed by other operations as known in the art. It will be appreciated that other transfer molding apparatus configurations, as well as variations in the details of the described method, are known in the art.
Undesirably, encapsulant flow during conventional transfer molding within mold cavities is demonstrably nonuniform. Therefore, encapsulant filler particles may become lodged between lead ends and the underlying die surfaces because the flow characteristics of the viscous encapsulant flow may cause particles to be forcefully driven between the lead ends and the additional surfaces of the semiconductor die and wedged or jammed in place in low-clearance areas. As the encapsulant flow front advances and the mold operation is completed by packing the cavities, pressure in substantially all portions of the mold cavities may be substantially hydrostatic. With LOC arrangements, where lead ends extending over the active surface of a die are bonded thereto by adhesive-coated tape segments or an adhesive material patterned on the active surface, the relative inflexibility of the tightly-constrained (adhered) lead ends maintains the point stresses of any particles trapped under the lead ends. These residual stresses are carried forward in the fabrication process to post-cure and beyond. When mechanical, thermal or electrical stresses attendant to post-encapsulation processing are added to the residual stresses associated with the lodged filler particles, cracking or perforation of the die coat may occur. It has been observed that filler particle-induced damage may occur more frequently in close proximity to the adhesive, where lead flexibility is relatively low. In addition to damage by filler particles, transfer molding also results in the problem of bond wire sweep, wherein bond wires may be damaged, broken, or loosened from their connections to bond pads or lead ends, or swept into shorting contact with an adjacent bond wire under the impetus of the flow front of molten resin encapsulant as it flows through a mold cavity. Also, due to increased pressures exerted on the encapsulant, a small amount of the encapsulation material often may flash between the mold halves, which may interfere with handling or require removal.
In addition to end-product deficiencies as noted above due to the phenomena of particulate die coat penetration, flash formation, and bond wire sweep, the capital-intensive nature of the transfer molding apparatus, including the requirement for different, relatively expensive molds for each die and lead frame or other substrate arrangement, as well as the high cost of the encapsulant resin and waste of same that is not used in the mold cavities, renders the transfer molding process an extremely expensive one. Mold damage and refurbishment is an additional, ongoing cost. Further, the elevated temperatures used in the molding process, as well as in the post cure of the resin encapsulant, are detrimental to the circuitry of the die as well as to the electrical connections to the lead ends.
Accordingly, the prior art has developed nonmolding encapsulation techniques for surrounding and at least partially sealing semiconductor dice. For instance, U.S. Pat. No. 6,549,821 to Farnworth et al., assigned to the assignee of the present invention and the disclosure of which is incorporated herein in its entirety by reference thereto, discloses a method and apparatus for applying packaging material to workpieces, particularly electronic components including semiconductor dice.
In addition, U.S. Pat. No. 6,537,482 to Farnworth, assigned to the assignee of the present invention and the disclosure of which is incorporated herein in its entirety by reference thereto, discloses a method for underfilling and encapsulating flip-chip configured semiconductor devices mounted on a carrier substrate using stereolithography to form at least semisolid dam structures of photopolymeric material to entrap unpolymerized resin between the devices and substrate.
However, in either of the above-mentioned conventional stereolithography approaches to encapsulation of semiconductor dice, the need for forming a multitude of relatively thin layers stereolithographically may be time consuming and may also depend on precise placement of the semiconductor dice, or, alternatively, a vision system for detecting the position thereof. Thus, there remains a need for improved apparatus and methods for at least partially encapsulating semiconductor dice without performing transfer molding.
Turning to another facet of conventional electronic fabrication techniques, conventional conductive traces may be formed by CVD processes, cold-metal deposition processes, plating processes, or other conventional additive techniques in combination with resist and etching processes, by way of solder paste deposited through a stencil, or by way of selective removal of copper from a copper dielectric laminate, as by masking and etching or other conventional subtractive techniques.
In relation to semiconductor dice, tape automated bonding (TAB) is sometimes used to form an electrical connection between the unpackaged die and external circuitry on a circuit board or other substrate. A TAB tape includes a flexible film, such as polyimide, having circuit traces formed thereon. The circuit traces may include bumps that are adapted for electrical connection to the bond pads on a die. The bumps and the circuit traces on the TAB tape provide an electrical path from the bond pads of the semiconductor die to external circuitry.
Also, circuit boards are often assembled with semiconductor devices to electrically connect different semiconductor devices to one another or to other components of an electronic device. Typically, circuit boards have one or more layers of metal circuitry carried by the insulating, or dielectric, substrates thereof. When circuit boards have conductive circuits extending across more than one plane thereof, the circuits may be electrically connected by way of through holes or blind holes that are metal plated or filled, which are known as conductive “vias.”
U.S. Pat. Nos. 6,500,746 and 6,632,732 to Williams, each assigned to the assignee of the present invention and the disclosure of each of which is incorporated herein in its entirety, each discloses stereolithographically fabricated conductive elements that may be formed onto circuit boards or chip scale packages. The patents also disclose that conductive traces, bond pads, and conductive vias may be formed stereolithographically. Further, U.S. Pat. No. 6,251,488 to Miller et al. discloses a precision spray process wherein metal particles are propelled toward a surface and heated while in flight toward the surface by a laser beam.
However, while the prior art methods may function as intended for forming conductive elements, there is a need for improved apparatus and methods for forming conductive elements, such as traces, bond pads, and conductive vias that are associated with electronic devices, such as circuit boards, or upon other substrates.
Moving to a further aspect of the prior art, it is known in the art to use a microlens array in combination with an imager array, such as a CMOS imager array, wherein the microlens array comprises a convex microlens associated with each pixel or the CMOS imager. Each microlens is configured to refract incident radiation from the circuitry region of the pixel to the photosensor region of the CMOS imager, thereby increasing the amount of light reaching the photosensor and increasing the fill factor of the pixels. Other uses of microlens arrays may include intensifying illuminating light on the pixels of a nonluminescent display device, such as a liquid crystal display device to increase the brightness of the display, forming an image to be printed in a liquid crystal or light emitting diode printer and as a focusing structure for coupling a luminescent device or a receptive device to an optical fiber.
Conventionally, a microlens or microlens array may be formed by depositing a microlens material layer by spin coating onto a surface of a semiconductor structure, in general alignment with a photosensor region thereof. The microlens areas may be patterned by a conventional photolithographic method, such as, for instance, a resist and etch process, and then may be subjected to increased temperature by a reflow process, for instance, at a temperature of about 160° Celsius. More specifically, the temperature may exceed the glass transition temperature of the microlens material, so that the upper surface area thereof forms an arcuate or domed surface, according to the surface tension or cohesive forces in the microlens material. A microlens may be formed of a transparent material exhibiting a suitable refractive index. For instance, a microlens may comprise an optical thermoplastic, such as polymethylmethacrylate, polycarbonate, polyolefin, cellulose acetate butyrate, polystyrene, or polyimide; a thermoset resin such as an epoxy resin; a photosensitive gelatin; or a radiation curable resin, such as acrylate, methacrylate, urethane acrylate, epoxy acrylate, or polyester acrylate.
U.S. Pat. No. 6,307,243 to Rhodes, assigned to the assignee of the present invention and the disclosure of which is incorporated herein in its entirety by reference thereto, discloses a microlens array for use in a solid-state imager having an improved fill factor. More specifically, an insulation layer is formed of transparent insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride, above each microlens in order to capture more light at the pixel edges and transmit such light to the photosensor, thereby improving the fill factor of the microlens array.
However, there is a need for improved apparatus and methods for forming one or more microlens structures. Particularly, there is a need for improved apparatus and methods for forming one or more microlens structures that are associated with image arrays, such as CMOS imagers.